The present invention is related to store operations in a virtual memory, and more particularly relates to providing single cycle store operations in a virtual memory of a data processing system.
In a data processing system including a central processor making stores to a virtual memory, the address of data to be stored in the memory must be translated from a virtual address to a real address. If the central processor has a pipeline, the pipeline must be blocked during the translation time. The present invention reduces store operations to only one cycle, thus improving the performance of move-type commands. This improvement can be from about twelve percent to about fifty percent, depending on the length of the field being moved. Since move-type commands are among the most frequently used commands, the optimization of these commands results in higher performance of the computer system.
U.S. Pat. No. 3,781,808 to Ahearn et al. for "Virtual Memory System", issued Dec. 25, 1973, discloses a virtual memory system having a Directory Look Aside Table for containing previously translated real addresses so that virtual addresses do not have to be translated over and over again.
U.S. Pat. No. 4,298,927 to Berglund et al. for "Computer Instructions Prefetch Circuit", issued Nov. 3, 1981, discloses a digital computer system including a main store, a virtual address translator, a microinstruction control unit and an instruction code prefetch circuit. The instruction code prefetch circuit retrieves the user instruction codes from the main store and holds them in a register until they are used. Designated microinstructions include commands which activate the instruction code prefetch circuit to retrieve the succeeding user instruction codes from the main store.
U.S. Pat. No. 4,332,010 to Messina et al. for "Cache Synonym Detection and Handling Mechanism", issued May 25, 1982, discloses a fast synonym detection and handling mechanism for a cache directory utilizing virtual addressing in data processing systems. Absolute addresses are translated from dynamic lookaside address translators, and a synonym detection circuit is used to interpret all directory compare signals to determine if a principal hit, a synonym hit or a miss occurred in the cache for each request.
U.S. Pat. No. 4,356,549 to Chueh for "System Page Table Apparatus", issued Oct. 26, 1982, discloses an apparatus for dynamically translating virtual memory addresses to real memory addresses, and includes a page fault circuit.
U.S. Pat. No. 4,376,297 to Anderson et al. for "Virtual Memory Addressing Device", issued Mar. 8, 1983, discloses a dynamic address translating unit for converting virtual or logical address values into real or physical address values.
U.S. Pat. No. 4,400,770 to Chan et al. for "Cache Synonym Detection and Handling Means", issued Aug. 23, 1983, discloses a device for eetecting and handling synonyms for a store-in-cache for fetching or storing operations.